Logical AND (DWORD)
Instruction Parameters
Supported PLC Series
| XPnA/1R | XPnB | XPnE | XPnF | CP3A/B/P/U CP4A~D/U | CPnE | CPnF | BP | PLC-S |
|---|---|---|---|---|---|---|---|---|
| ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Supported Data Registers
| M | X | Y | K | L | F | T | C | S | Z | R | Q | D | @D | Constant | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| S1 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | - | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
| S2 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | - | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
| D | ✓ | - | ✓ | ✓ | ✓ | - | ✓ | ✓ | - | ✓ | ✓ | ✓ | ✓ | ✓ | - |
Supported Flags
| Flag | Bit | Support |
|---|---|---|
| Error | F11.0 | ✓ |
| Zero | F11.1 | ✓ |
| Carry | F11.2 | - |
Number of Steps
| Steps |
|---|
| 4 |
Operands
| Operand | Description |
|---|---|
| S1 | The first operand. Entries are DWORD data registers or constants. The signed value range is -2,147,483,648 ~ 2,147,483,647 (232). The unsigned value range is 0 ~ 4,294,967,295 (232-1). The Hexadecimal value range is H00000000 ~ HFFFFFFFF. |
| S2 | The second operand. Entries are DWORD data registers or constants. The signed value range is -2,147,483,648 ~ 2,147,483,647 (232). The unsigned value range is 0 ~ 4,294,967,295 (232-1). The Hexadecimal value range is H00000000 ~ HFFFFFFFF. |
| D | The third operand. Entries are only DWORD data registers. This is where the result of a logical S1 AND S2 is saved. |
Notice
Error Flag (F11.0) Notice
The error flag, F11.0, will be ON for one scan when the address of the data register assigned by @D exceeds the range of the data register, D. The range of the data register, D, is dependent on the CPU type.
F11.0 turns ON when the value of the data for a logical AND exceeds the data register assigned to S1 or S2.
Zero Flag (F11.1) Notice
The zero flag, F11.1, will be ON for one scan when the logical operation result is 0.
This occurs only when the DAND or DANDP instructions are executed with a CP3A/B/P/U or CP4A~D/U PLC.
Logical Operation
The DAND and DANDP instructions perform a logical AND on each bit of S1 and S2.
