Logical AND (Block)
Instruction Parameters
Supported PLC Series
| XPnA/1R | XPnB | XPnE | XPnF | CP3A/B/P/U CP4A~D/U | CPnE | CPnF | BP | PLC-S |
|---|---|---|---|---|---|---|---|---|
| ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Supported Data Registers
| M | X | Y | K | L | F | T | C | S | Z | R | Q | D | @D | Constant | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| S1 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | - | ✓ | - | ✓ | ✓ | ✓ | - |
| S2 | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | - | ✓ | - | ✓ | ✓ | ✓ | ✓ |
| D | ✓ | - | ✓ | ✓ | ✓ | - | ✓ | ✓ | - | ✓ | - | ✓ | ✓ | ✓ | - |
| n | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | - | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ |
Supported Flags
| Flag | Bit | Support |
|---|---|---|
| Error | F11.0 | ✓ |
| Zero | F11.1 | - |
| Carry | F11.2 | - |
Number of Steps
| Steps |
|---|
| 5 |
Operands
| Operand | Description |
|---|---|
| S1 | The first operand. Entries are only WORD data registers. The signed value range is for each data register -32,768 ~ 32,767 (216). The unsigned value range for each data register is 0 ~ 65,535 (216-1). The Hexadecimal value range for each data register is H0000 ~ HFFFF. |
| S2 | The second operand. Entries are WORD data registers or constants. The signed value range for each data register is -32,768 ~ 32,767 (216). The unsigned value for each data register range is 0 ~ 65,535 (216-1). The Hexadecimal value for each data register range is H0000 ~ HFFFF. |
| D | The third operand. Entries are only WORD data registers. This is where the result of a logical S1 AND S2 is saved. |
| n | The fourth operand. Entries are WORD data registers or constants. This is the amount of words for a logical S1 ~ Sn AND S2 ~ Sn. |
Notice
Error Flag (F11.0) Notice
The error flag, F11.0, will be ON for one scan when the address of the data register assigned by @D exceeds the range of the data register, D. The range of the data register, D, is dependent on the CPU type.
F11.0 turns ON when the value of the data for a logical AND exceeds the data register assigned to S1 or S2.
Logical Operation
The BKAND and BKANDP instructions will perform a logical AND on each bit of the data registers between S1 ~ Sn and S2 ~ Sn.
