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CM3 PWM Module Buffer Memory

To write to buffer memory, use the TO instruction.

To read from buffer memory, use the FROM instruction.

Please refer to the table below for writing to and reading from buffer memory.

The CM3-SP32PWM expansion module reserves 64 WORDs of buffer memory.

CM3-SP32PWM Buffer Memory
Memory AddressDetailsReadWrite
HexadecimalDecimal
00H0PWM Output Enable✓✓
01H1Frequency
Channels 1, 2, 3, and 4		✓✓
02H2Frequency
Channels 5, 6, 7, and 8		✓✓
03H3Frequency
Channels 9, 10, 11, and 12		✓✓
04H4Reserved--
05H5Frequency RAMP Control Time
Channels 1, 2, 3, and 4		✓✓
06H6Frequency RAMP Control Time
Channels 5, 6, 7, and 8		✓✓
07H7Frequency RAMP Control Time
Channels 9, 10, 11, and 12		✓✓
08H8Reserved--
09H9Error Code✓-
0AH10Channel 1 DUTY Cycle Ratio✓✓
0BH11Channel 2 DUTY Cycle Ratio✓✓
0CH12Channel 3 DUTY Cycle Ratio✓✓
0DH13Channel 4 DUTY Cycle Ratio✓✓
0EH14Channel 5 DUTY Cycle Ratio✓✓
0FH15Channel 6 DUTY Cycle Ratio✓✓
10H16Channel 7 DUTY Cycle Ratio✓✓
11H17Channel 8 DUTY Cycle Ratio✓✓
12H18Channel 9 DUTY Cycle Ratio✓✓
13H19Channel 10 DUTY Cycle Ratio✓✓
14H20Channel 11 DUTY Cycle Ratio✓✓
15H21Channel 12 DUTY Cycle Ratio✓✓
16H22Reserved--
17H23--
18H24--
19H25--
1AH26--
1BH27--
1CH28--
1DH29--
1EH30Channel 1 DUTY Cycle RAMP Time (× 10ms)✓✓
1FH31Channel 2 DUTY Cycle RAMP Time (× 10ms)✓✓
20H32Channel 3 DUTY Cycle RAMP Time (× 10ms)✓✓
21H33Channel 4 DUTY Cycle RAMP Time (× 10ms)✓✓
22H34Channel 5 DUTY Cycle RAMP Time (× 10ms)✓✓
23H35Channel 6 DUTY Cycle RAMP Time (× 10ms)✓✓
24H36Channel 7 DUTY Cycle RAMP Time (× 10ms)✓✓
25H37Channel 8 DUTY Cycle RAMP Time (× 10ms)✓✓
26H38Channel 9 DUTY Cycle RAMP Time (× 10ms)✓✓
27H39Channel 10 DUTY Cycle RAMP Time (× 10ms)✓✓
28H40Channel 11 DUTY Cycle RAMP Time (× 10ms)✓✓
29H41Channel 12 DUTY Cycle RAMP Time (× 10ms)✓✓
2AH42Reserved--
2BH43--
2CH44--
2DH45--
2EH46--
2FH47--
30H48--
31H49--
32H50--
33H51--
34H52--
35H53--
36H54--
37H55--
38H56--
39H57--
3AH58--
3BH59--
3CH60--
3DH61--
3EH62--
3FH63OS Version--

Pulse-Width Modulation Output Enable​

  • The pulse-width modulation output enable will enable the channels for pulse-width modulation when set to 1 or general digital output when set to 0.
  • The PWM output function can be enabled by using the TO instruction.
PWM Channel Enable Bit Mapping
Buffer Memory 0Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8Bit 9Bit 10Bit 11Bit 12Bit 13Bit 14Bit 15
Channel NumberChannel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8Channel 9Channel 10Channel 11Channel 12ReservedReservedReservedReserved

Frequency Control​

  • The pulse-width modulation supports functions to control the frequency range from 0 ~ 4,000pps.
    • 4 channels per group can be controlled.
      • A total of 3 groups can be controlled.
  • The frequencies of each group are set by the TO instruction.
Frequency Control
Frequency A or General Digital OutputFrequency B or General Digital OutputFrequency C or General Digital Output
Channel 1Yn.2Channel 5Yn.AChannel 9Yn+1.2
Channel 2Yn.3Channel 6Yn.BChannel 10Yn+1.3
Channel 3Yn.6Channel 7Yn.CChannel 11Yn+1.4
Channel 4Yn.7Channel 8Yn.DChannel 12Yn+1.5
  • Every 4 PWM output included in a group are operated in the same frequency.
  • 3 different frequency outputs are available at the same time since 3 groups are offered.
  • When the TO instruction is operated on the buffer memory, the output terminal outputs the designated frequency instantly.
  • If the frequency value is over 4,000pps, both the valid range f the DUTY cycle and degree of precision are decreased.
Frequency Precision Values
Frequency (pps)Minimum Value of DUTY Cycle (%)Maximum Value of DUTY Cycle (%)
5,0001.098.0
10,0001.595.0
15,0003.094.0
20,0004.093.0
25,0005.091.0
30,0006.089.0
35,0007.087.0
40,0009.085.0
45,00010.083.0
50,00012.082.0
55,00013.080.0
60,00014.078.0
65,00015.075.0

RAMP Control​

  • RAMP control can be used to prevent a sharp change of the frequency and DUTY cycle.
  • The output will be gradually changed during the RAMP control time, which the value of the frequency or DUTY cycle have configured.
  • When the set value of the RAMP control time of buffer memory is 0, output will be changed immediately.
  • The following is a method for RAMP control:
    • Change the RAMP control time before the value to control as intended.
    • In case of a power reset or CPU STOP during the RAMP operation, reset the value again by using the TO instruction.
      • The value of the buffer memory will be set back to the initial value, 0.

Frequency RAMP Control Time​


  • The frequency will be changed through the set RAMP control time when the frequency value is changed after setting the frequency RAMP control time.
  • The frequency RAMP control time can be set by using the TO instruction.
  • In case the frequency RAMP control time is changed during the RAMP operation, it will be applied to the NEXT RAMP operation.
  • In case of a power reset or CPU STOP during the RAMP operation, reset the value again by using the TO instruction.

Controlling DUTY Cycle​

  • The pulse-width modulation supports functions to control the DUTY cycle 0.0% ~ 100.0% within 1/1,000 resolution.
  • The DUTY cycles are able to be controlled per channel for a total of 12 channels.
  • The DUTY cycle can be set using the TO instruction.
  • When the TO instruction is operated, the output terminal will be configured to set the DUTY cycle and being output.


  • If the digital signal of +12V-+24V voltage is set to the DUTY cycle 70.0% (as shown above), the voltage output of +8.4V-+16.8V in average is available.
  • The DUTY cycle control (PWM) can be utilized in various ways of substituting an analog signal.
    • Controlling the speed of a motor, switch, or ratio of a value are examples.

DUTY Cycle RAMP Control​


  • If the DUTY cycle's value is configured after setting the DUTY cycle RAMP control time, the DUTY cycle will be gradually changed during the set RAMP control time.
  • The DUTY cycle ratio can be set using the TO instruction.
    • In case the DUTY cycle ramp control time is configured during the AMP operation, it will be applied to the NEXT RAMP operation.
    • In case of a power reset or CPU STOP during the RAMP operation, reset the value again by using the TO instruction.
      • The value of the buffer memory will be set back to the initial value, 0.