CM3 RTD Module Internal I/O Table

CM3-SP04ERO Internal I/O Table

CM3-SP04ERO Internal I/O Signal Table
Direction of Signal CM3-SP04ERO → CPU		Direction of Signal CPU → CM3-SP04ERO
Input	Name of Signal	Output	Name of Signal
Xn.0	RTD Module Ready	Yn.0	Reserved
Xn.1	RTD conversion completion flag	Yn.1
Xn.2	Set value saving completion flag	Yn.2	Requesting to save set value
Xn.3	Reserved	Yn.3	Reserved
Xn.4		Yn.4
Xn.5		Yn.5
Xn.6		Yn.6
Xn.7		Yn.7
Xn.8		Yn.8
Xn.9		Yn.9
Xn.A		Yn.A
Xn.B		Yn.B
Xn.C		Yn.C
Xn.D		Yn.D
Xn.E		Yn.E	Requesting circuit calibration
Xn.F	RTD Module Error Flag	Yn.F	Requesting to Clear Error Flag

Input Signal

Input Signal
Data Register	Signal Name	Description
Xn.0	RTD Module Ready	This signal is turned ON at the time RTD conversion is completely ready (CPU power is ON).
Xn.1	RTD conversion completion flag	If any conversion-enabled channel is not converted more than 1 time while the PLC power is ON and its initialization is completed, the flag is OFF. If all conversion-enabled channels finish converting more than one time, the flag is ON. If the set value is changed, this flag is cleared.
Xn.2	Set value saving completion flag	This flag is used for interlocking to turn ON/OFF the Requesting to save set value (Yn.2) data register when RTD conversion enable/disable is changed. If Set value saving completion flag is OFF, the RTD conversion process is not performed.
Xn.F	RTD module error flag	This flag is turned ON when an error occurs in the module. Error code clear turns the Requesting to clear error (Yn.F) data register ON.

Output Signal

Output Signal
Data Register	Signal Name	Description
Yn.2	Requesting to save set value	This signal is turned ON when RTD conversion enable/disable, RTD set data, and minimum and maximum temperature set value are stored. Refer to Set value saving completion (Xn.2) for timing of ON/OFF.
Yn.E	Requesting circuit calibration	This signal is turned ON when circuit calibration is requested. Refer to Set value saving completion (Xn.2) for timing of ON/OFF.
Yn.F	Requesting to clear error	This signal is turned ON when the error flag, Xn.F, is cleared. Refer to RTD module error flag (Xn.F) for timing of ON/OFF.

Allocation Example

The CM3-SP04ERO is allocated one WORD of X (Xn.0 ~ Xn.F) and one WORD of Y (Yn.0 ~ Yn.F).

n is a number representing the CM3-SP04ERO's position within the chassis.

To access the X memory registers for this CM3-SP04ERO example, the X value range is X2.0 ~ X2.F.
To access the Y memory registers for this CM3-SP04ERO example, the Y value range is Y2.0 ~ Y2.F.